2.54 0.2 8-0.6 2.5 min 0.5 0.5 0.5 14 2.54 (=35.56) heat sink side 18 3 min 12 2-r1.6 0.28 25 4-c1.2 t ype name lot no. qr code 24 0.5 9.5 0.5 5.5 0.5 (1) terminal code 1. (vnc) 2. v ufb 3. v vfb 4. v wfb 5. u p 6. v p 7. w p 8. v p1 9. v nc * 10. u n 11. v n 12. w n 13. v n1 14. f o 15. cin 16. v nc * 17. nc 18. nc 19. nc 20. n 21. w 22. v 23. u 24. p 25. nc 29.2 0.5 14.4 0.5 14.4 0.5 (3.5) (3.3) heat sink side 0.4 0.4 1.5 0.05 3.5 b 0.8 (2.656) (2.756) (0~5 ) (1.2) (1.2) detail a detail b 0.28 1.778 0.2 35 0.3 20 1.778(=35.56) 38 0.5 17 1 a 16-0.5 0.5 1.5 min ps21993-4e integrated power functions 600v/8a low-loss cstbt inverter bridge for three phase dc-to-ac power conversion application ac100v~200v three-phase inverter drive for small power motor control. fig. 1 package outlines (ps21993-4e) mitsubishi semiconductor ps21993-4e/-4ae/-4ce/-4ew transfer-mold type insulated type integrated drive, protection and system control functions for p-side : drive circuit, high voltage high-speed level shifting, control supply under-voltage (uv) protection. for n-side : drive circuit, control supply under-voltage protection (uv), short circuit protection (sc). fault signaling : corresponding to a sc fault (n-side igbt), a uv fault (n-side supply). input interface : 3~5v line (high active). ? l recognized : yellow card no. e80276 dimensions in mm *) two v nc terminals (9 & 16 pin) are connected inside dipipm, please connect either one to the 15v power supply gnd outside and leave another one open. sep. 2008 note : cstbt is registered trademark of mitsubishi electric corporation in japan.
mitsubishi semiconductor ps21993-4e/-4ae/-4ce/-4ew transfer-mold type insulated type sep. 2008 2 fig. 2 long terminal type package outlines (PS21993-4AE) fig. 3 zigzag terminal type package outlines (ps21993-4ce) 2.54 0.2 8-0.6 2.5 min 14 2.54 (=35.56) heat sink side 18 3 min 12 2-r1.6 0.28 25 4-c1.2 t ype name lot no. qr code 24 0.5 14 0.5 5.5 0.5 (1) terminal code 1. (vnc) 2. v ufb 3. v vfb 4. v wfb 5. u p 6. v p 7. w p 8. v p1 9. v nc * 10. u n 11. v n 12. w n 13. v n1 14. f o 15. cin 16. v nc * 17. nc 18. nc 19. nc 20. n 21. w 22. v 23. u 24. p 25. nc 29.4 0.5 14.4 0.5 14.4 0.5 (3.5) (3.3) heat sink side 0.4 0.4 1.5 0.05 3.5 b 0.8 (2.656) (2.756) (0~5 ) (1.2) (1.2) detail a detail b 0.28 1.778 0.2 35 0.3 20 1.778(=35.56) 38 0.5 17 1 a 16-0.5 1.5 min 0.5 0.5 0.5 0.5 2.54 0.2 8-0.6 14 2.54 (=35.56) heat sink side 18 3 min 12 2 -r 1 .6 0.28 25 4-c1.2 t ype name lot no. qr code 24 0.5 9.5 0.5 5.5 0.5 (1) terminal code 1. (vnc) 2. v ufb 3. v vfb 4. v wfb 5. u p 6. v p 7. w p 8. v p1 9. v nc * 10. u n 11. v n 12. w n 13. v n1 14. f o 15. cin 16. v nc * 17. nc 18. nc 19. nc 20. n 21. w 22. v 23. u 24. p 25. nc 29.2 0.5 33.7 0.5 14.4 0.5 18.9 0.5 14.4 0.5 (3.5) heat sink side 0.4 0.4 1.5 0.05 3.5 b 0.8 detail b 0.28 1.778 0.2 35 0.3 20 1.778(=35.56) 38 0.5 17 1 a 0.4 0.5 1.5 min (0~5 ) (0~5 ) 16-0.5 0.5 0.5 (2.656) (2.756) (1.2) (1.2) detail a dimensions in mm dimensions in mm *) two v nc terminals (9 & 16 pin) are connected inside dipipm, please connect either one to the 15v power supply gnd outside and leave another one open. *) two v nc terminals (9 & 16 pin) are connected inside dipipm, please connect either one to the 15v power supply gnd outside and leave another one open.
mitsubishi semiconductor ps21993-4e/-4ae/-4ce/-4ew transfer-mold type insulated type sep. 2008 3 2.54 0.25 7-0.6 2.5 min 14 2.54 (=35.56) heat sink side 18 3 min 12 (1.8) 2-r1.6 0.28 25 4-c1.2 t ype name lot no. qr code 24 0.5 11 0.5 5.5 0.5 (1) terminal code 1. (vnc) 2. v ufb 3. v vfb 4. v wfb 5. u p 6. v p 7. w p 8. v p1 9. v nc * 10. u n 11. v n 12. w n 13. v n1 14. f o 15. cin 16. v nc * 17. nc 18. nc 19. nc 20. n 21. w 22. v 23. u 24. p 25. nc 35.2 0.6 29.2 0.5 14.4 0.5 14.4 0.5 17.4 0.5 17.4 0.5 (3.5) heat sink side 0.4 1.5 0.05 3.5 b 0.8 0.4 0.4 (2.656) (2.756) (0~5 ) (1.2) (1.2) detail a detail b 0.28 1.778 0.25 35 0.3 20 1.778(=35.56) 38 0.5 17 1 a 16-0.5 0.4 1.5 min (0~5 ) 0.5 0.5 0.5 m c1 : electrolytic type with good temperature and frequency characteristics. the capacitance also depends on the pwm control strategy of the application system. c2 : 0.22 -2 f ceramic capacitor with good temperature, frequency and dc bias characteristics. d1 : bootstrap diode (v rrm =600v or more. trr=100ns or less) d2 : zener diode (24v/1w) z : surge absorber c : ac filter(ceramic capacitor 2.2n -6.5nf) (common-mode noise filter) uv lockout circuit drive circuit ac line input input signal conditioning input signal conditioning input signal conditioning level shift drive circuit level shift drive circuit level shift drive circuit input signal conditioning protection circuit (sc) uv lockout circuit f o dipipm inrush limiting circuit v d c1 c2 d2 v nc p-side igbt s n-side igbt s w v u c2 c1 d2 d1 p v nc n1 n cin z c p-side input (pwm) (15v line) ac output f o output (5v line) n-side input (pwm) fo logic fig. 5 internal functions block diagram (typical application example) fig. 4 both sides zigzag terminal type package outlines (ps21993-4ew) dimensions in mm *) two v nc terminals (9 & 16 pin) are connected inside dipipm, please connect either one to the 15v power supply gnd outside and leave another one open. qr code is registered trademark of denso wave incorporated in japan and other countries.
mitsubishi semiconductor ps21993-4e/-4ae/-4ce/-4ew transfer-mold type insulated type sep. 2008 4 v v v v ma v 20 20 ?.5~v d +0.5 ?.5~v d +0.5 1 ?.5~v d +0.5 applied between v p1 -v nc , v n1 -v nc applied between v ufb -u, v vfb -v, v wfb -w applied between u p , v p , w p , u n , v n , w n -v nc applied between f o -v nc sink current at f o terminal applied between cin-v nc control supply voltage control supply voltage input voltage fault output supply voltage fault output current current sensing input voltage v d v db v in v fo i fo v sc 450 500 600 8 16 24.3 ?0~+125 applied between p-n applied between p-n t c = 25 c t c = 25 c, less than 1ms t c = 25 c, per 1 chip (note 1) v cc v cc(surge) v ces i c i cp p c t j condition symbol parameter ratings unit supply voltage supply voltage (surge) collector-emitter voltage each igbt collector current each igbt collector current (peak) collector dissipation junction temperature v v v a a w c maximum ratings (t j = 25 c, unless otherwise noted) inverter part condition symbol parameter ratings unit control (protection) part note 1 : the maximum junction temperature rating of the power chips integrated within the dipipm is 150 c (@ t c 100 c). however, to ensure safe operation of the dipipm, the average junction temperature should be limited to t j(ave) 125 c (@ t c 100 c). note1: in the recommended external protection circuit, please select the rc time constant in the range 1.5~2.0 s. 2: to prevent erroneous protection operation, the wiring of a, b, c should be as short as possible. drive circuit drive circuit protection circuit w v u b c v nc cin a p n1 n c r shunt resistor external protection circuit dipipm n-side igbt s p-side igbt s sc protection trip level i c (a) t w ( s) 2 0 short circuit protective function (sc) : sc protection is achieved by sensing the n-side dc-bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the rc circuit). when the sensed shunt voltage exceeds the sc trip-level, all the n-side igbts are turned off and a fault signal (fo) is output. since the sc fault may be repetitive, it is recommended to stop the system when the fo signal is received and check the fault. collector current waveform (note 1) (note 2) fig. 6 external part of the dipipm protection circuit
mitsubishi semiconductor ps21993-4e/-4ae/-4ce/-4ew transfer-mold type insulated type sep. 2008 5 2.10 2.20 2.35 1.70 0.60 2.35 1.00 1 10 4.1 5.4 ma v t j = 25 c t j = 125 c i c = 8a, t j = 25 c i c = 8a, t j = 125 c v ce(sat) v ec t on t rr t c(on) t off t c(off) i ces condition symbol parameter limits inverter igbt part (per 1/6 module) inverter fwdi part (per 1/6 module) r th(j-c)q r th(j-c)f min. thermal resistance t yp. max. unit t j = 25 c, ? c = 8a, v in = 0v condition symbol parameter limits min. t yp. max. 0.60 unit electrical characteristics (t j = 25 c, unless otherwise noted) inverter part collector-emitter saturation voltage fwdi forward voltage junction to case thermal resistance (note 3) v d = v db = 15v v in = 5v switching times v cc = 300v, v d = v db = 15v i c = 8a, t j = 125 c, v in = 0 ? 5v inductive load (upper-lower arm) collector-emitter cut-off current v ce = v ces 1.60 1.70 1.90 1.10 0.30 0.40 1.50 0.40 v s s s s s c/w c/w note 3 : grease with good thermal conductivity and long-term quality should be applied evenly with +100 m~+200 m on the contacting surface of dipipm and heat sink. the contacting thermal resistance between case and heat sink (r th(c-f) ) is determined by the thickness and the thermal conductivity of the applied grease. for reference, r th(c-f) (per 1/6 module) is about 0.3 c/w when the grease thickness is 20 m and the thermal conductivity is 1.0w/mk. dipipm igbt chip position power terminals fwdi chip position control terminals t c point heat sink side 11.6mm 3mm 400 ?0~+100 ?0~+125 1500 v d = 13.5~16.5v, inverter part t j = 125 c, non-repetitive, less than 2 s (note 2) 60hz, sinusoidal, 1 minute, between pins and heat sink plate v cc(prot) t c t stg v iso symbol ratings unit self protection supply voltage limit (short circuit protection capability) module case operation temperature storage temperature isolation voltage v c c v rms to ta l system parameter condition note 2: t c measurement point
mitsubishi semiconductor ps21993-4e/-4ae/-4ce/-4ew transfer-mold type insulated type sep. 2008 6 control (protection) part note 4 : short circuit protection works only for the n-side. please select the external shunt resistance such that the sc trip-level is up to 1.7 times of the current rating. 5: fault signal is asserted only corresponding to a sc or a uv failure at n-side, and the fo pulse width is different for each fai lure modes. for sc failure, fo output is with a fixed width of 20 s(min), but for uv failure, fo outputs continuously during the whole uv period, however, the minimum fo pulse width is 20 s(min) for very short uv period less than 20 s. symbol i d v foh v fol v sc(ref) i in uv dbt uv dbr uv dt uv dr t fo v th(on) v th(off) v th(hys) parameter condition limits unit v d = v db = 15v v in = 5v v sc = 0v, f o terminal pull-up to 5v by 10k ? v sc = 1v, i fo = 1ma v d = 15v (note 4) v in = 5v t rip level reset level t rip level reset level (note 5) applied between u p , v p , w p , u n , v n , w n -v nc 4.9 0.43 0.70 10.0 10.5 10.3 10.8 20 0.8 0.35 0.48 1.00 2.1 1.3 0.65 2.80 0.55 2.80 0.55 0.95 0.53 1.50 12.0 12.5 12.5 13.0 2.6 min. typ. max. ma ma ma ma v v v ma v v v v s v v v v d = v db = 15v v in = 0v t j 125 c circuit current fault output voltage short circuit trip level control supply under-voltage protection fault output pulse width on threshold voltage off threshold voltage on/off threshold hysteresis voltage t otal of v p1 -v nc , v n1 -v nc v ufb -u, v vfb -v, v wfb -w t otal of v p1 -v nc , v n1 -v nc v ufb -u, v vfb -v, v wfb -w input current note 7: flatness measurement position + + heat sink side heat sink side 4.6mm measurement position 17.5mm mounting screw : m3 ( note 6 ) condition parameter limits mounting torque w eight heat-sink flatness min. mechanical characteristics and ratings t yp. max. 0.59 ?0 unit 10 0.78 100 n? g m recommended : 0.69 n? ( note 7 ) note 6 : plain washers (iso 7089~7094) are recommended.
mitsubishi semiconductor ps21993-4e/-4ae/-4ce/-4ew transfer-mold type insulated type sep. 2008 7 fig. 7 the dipipm internal circuit u out v out u out v vs w out v ws v out w out v no gnd fo w n v n u n v cc hvic lvic cin cin n w v u p com v ub v us v cc v vb v p v wb w p fo w n v n u n w p v p u p u p v nc v n1 v p1 v vfb v wfb v nc v ufb igbt1 igbt2 igbt3 igbt4 igbt5 igbt6 di1 di2 di3 di4 di5 di6 v v v v/ s s khz supply voltage control supply voltage control supply voltage control supply variation arm shoot-through blocking time pwm input frequency applied between p-n applied between v p1 -v nc , v n1 -v nc applied between v ufb -u, v vfb -v, v wfb -w for each input signal, t c 100 c t c 100 c, tj 125 c 400 16.5 18.5 1 20 v cc v d v db ? v d , ? v db t dead f pwm condition symbol parameter limits min. t yp. max. 0 13.5 13.0 ? 1.5 unit recommended operation conditions 300 15.0 15.0 note 8 : the allowable rms current value depends on the actual application conditions. 9: ipm might not make response if the input signal pulse width is less than the recommended minimum value. i o pwin(on) pwin(off) v nc allowable rms current allowable minimum input pulse width v nc variation v cc = 300v, v d = v db = 15v, p .f = 0.8, sinusoidal pwm, t j 125 c, t c 100 c (note 8) (note 9) between v nc -n (including surge) arms s v 0.5 0.5 ?.0 5.0 f pwm = 5khz f pwm = 15khz 4.5 3.0
mitsubishi semiconductor ps21993-4e/-4ae/-4ce/-4ew transfer-mold type insulated type sep. 2008 8 error output fo output current ic control supply voltage v d protection circuit state control input b1 b2 b3 b5 reset reset uv dt uv dr set b6 b4 b7 protection circuit state n-side control input fault output fo sense voltage of the shunt resistor output current ic internal igbt gate sc reference voltage rc circuit time constant delay a5 a8 a4 a3 a1 a2 sc reset set a7 a6 fig. 8 timing chart of the protective functions [a] short-circuit protection (n-side only with the external shunt resistor and rc filter) a1. normal operation : igbt on and carrying current. a2. short circuit is detected (sc trigger). a3. all n-side igbts gates are hard interrupted. a4. all n-side igbts turn off. a5. f o is output (t fo(min) = 20 s). a6. input ?? a7. input ?? but igbt is still off state during outputting f o . a8. igbt turns on when l h signal is input after f o is reset. [b] under-voltage protection (n-side, uv d ) b1. control supply voltage v d rises : after v d level rises over under voltage reset level (uv dr ), the circuits start to operate when next input is applied. b2. normal operation : igbt on and carrying current. b3. v d level dips to under voltage trip level. (uv dt ). b4. all n-side igbts turn off in spite of control input condition. b5. f o is output. (t fo 20 s and f o outputs continuously during uv period). b6. v d level rises over uv dr . b7. normal operation : igbt on and carrying current.
mitsubishi semiconductor ps21993-4e/-4ae/-4ce/-4ew transfer-mold type insulated type sep. 2008 9 mcu 10k ? u p ,v p ,w p ,u n ,v n ,w n v nc (logic) fo dipipm 5v line 3.3k ? (min) error output fo output current ic control supply voltage v db protection circuit state control input c6 c1 c2 c4 c5 c3 reset uv dbt uv dbr set reset high-level (no fault output) [c] under-voltage protection (p-side, uv db ) c1. control supply voltage v db rises : after v db level rises over under voltage reset level (uv dbr ), the circuits start to operate when next input is applied. c2. normal operation : igbt on and carrying current. c3. v db level dips to under voltage trip level. (uv dbt ). c4. p-side igbt turns off in spite of control input signal level, but there is no f o signal output. c5. v db level rises over uv dbr . c6. normal operation : igbt on and carrying current. fig. 9 an instance of interface circuit note : the setting of rc coupling at each input (parts shown dotted) depends on the pwm control scheme and the wiring impedance of the printed circuit board. input circuit integrates a 3.3k ? (min) pull-down resistor. therefore, when using an external filtering resistor, pay attention to the turn-on threshold voltage. fig. 10 wiring connection of shunt resistor n dipipm wiring inductance should be less than 10nh. shunt resistor equivalent to the inductance of a copper pattern in dimension of width=3mm, thickness=100 m, length=17mm please connect gnd wiring from v nc terminal to the shunt resistor terminal as close as possible. v nc
mitsubishi semiconductor ps21993-4e/-4ae/-4ce/-4ew transfer-mold type insulated type sep. 2008 10 fig. 11 an example of typical dipipm application circuit 15v line w out v out c3 c2 c2 c2 c1 c1 c1 u out w p v wb v p v vb 5v line u p com u out v out w out gnd f o w n v n v cc c b a r1 n1 c4 cin n w v u p v ws v vs v us v ub v cc fo w n v n u n u n w p v p u p v nc v nc v n1 v p1 v ufb v vfb v wfb c3 mcu hvic lvic shunt resistor long wiring here might cause sc level fluctuation and malfunction. long gnd wiring here might generate noise to input and cause igbt malfunction. long wiring here might cause short-circuit. long wiring here might cause short-circuit. m m bootstrap negative electrodes should be connected to u, v, w terminals directly and separated from the main output wires. note 1 : input drive is high-active type. there is a 3.3k ? (min.) pull-down resistor in the input circuit of ic. to prevent malfunction, the wiring of each input should be as short as possible. when using rc coupling circuit, make sure the input signal level meet the turn-on an d turn- off threshold voltage. 2: thanks to hvic inside the module, direct coupling to mcu without any opto-coupler or transformer isolation is possible. 3: fo output is open drain type. it should be pulled up to the mcu or control power supply (e.g. 5v, 15v) by a resistor that makes i fo up to 1ma. 4: to prevent erroneous protection, the wiring of a, b, c should be as short as possible. 5: the time constant r1c4 of the protection circuit should be selected in the range of 1.5-2 s. sc interrupting time might vary with the wiring pattern. tight tolerance, temp-compensated type is recommended for r1, c4 6: all capacitors should be mounted as close to the terminals of dipipm as possible. (c1: good temperature, frequency characterist ic electrolytic type, and c2, c3 (0.22~2 f) : good temperature, frequency and dc bias characteristic ceramic type are recommended.) 7: to prevent surge destruction, the wiring between the smoothing capacitor and the p, n1 terminals should be as short as possible . generally a 0.1-0.22 f snubber between the p-n1 terminals is recommended. 8: t wo v nc terminals (9 & 16 pin) are connected inside dipipm, please connect either one to the 15v power supply gnd and leave the other open. 9: it is recommended to insert a zener diode (24v/1w) between each pair of control supply terminals to prevent surge destruction. 10 : if control gnd is connected with power gnd by common broad pattern, it may cause malfunction by power gnd fluctuation. it is recommended to connect control gnd and power gnd at only a point n1. 11 : high voltage (v rrm =600v or more) and fast recovery type (t rr =100ns or less) diodes should be used in the bootstrap circuit.
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